Compact modeling of memristors based on resistive switching devices

Resumen

In the current electronic industry there is a growing demand for temporary (volatile) and permanent (non-volatile) data storage, in portable devices this demand is even higher and also requires low power consumption. This memory needs become evident in smartphones, laptops, internet of things (IoT) devices, 5G circuits, solid-state drives (SSD), cloud storage, data mining, artificial intelligence, among others applications [Gupta2019]. RRAMs are the main memory emerging technology since it is the more viable alternative due to its ease of integration into the current CMOS technology in the Back-End-Of-Line (BEOL), good scalability, data retention, endurance, speed and latency, low energy consumption and the possibility of 3D integration and multibit programming. The dominant technology in the current solid state memory market is focused on static memories (SRAM), DRAM dynamic memories and Flash memories. The latter ones are non-volatile memories (Non-Volatile Memories, NVM), a memory that stores information when the power systems are turned off. In the context of NVM, different technological alternatives are being studied both at the academia and at the industry: RRAMs (Resistive Switching RAMs), PCM (Phase Change Memories) and STT-RAMs (Spin-Transfer Torque RAMs), which are being the subject of research in all large companies and research centres of the electronics sector actively [Xie2014]. This increase in R&D activities arises in a context where information storage is key in the electronic industry. The incessant increase in the amount of information circulating on the planet means that storage memory needs are increasingly more pressing and are conditioned by electronic systems that reduce their execution time (at the level of nanoseconds), which have low consumption of energy and retention times greater than ten years. There are two main reasons to focus research efforts on non-volatile memories: 1.- They have a great potential for growth if their main facet (non-volatility) is accompanied by a high switching speed, they could gain part of the market space currently occupied by the SRAM or DRAM volatile memories [Xie2014]. 2. - This type of memories are the key components of devices that mean almost half of the memory market currently [Xie2014]. Non-volatile memories based on silicon technology, Flash memory, have been used in mobile phones, video games, scientific instrumentation, industrial robotics, etc. Despite this, the technological limit for these devices is close and this is a very important hurdle [Gupta2019, Xie2014, Waser2007, Waser2012]. The RRAMs are well positioned candidates within emerging technologies in comparison to other alternatives such as magnetic memories MRAMs (Magnetic RAMs), STT-RAM memories or PCM memories [Lanza2019, Xie2014, Waser2007, Waser2012]. Resistive memories work making use of resistive switching (RS) phenomena, which were discovered in the early 60's. Many different materials show RS, i.e., switching with an hysteretic behaviour. Although the activity in these devices was reduced by the competence of (DRAM, EEPROM), it was retaken in the nineties. A great rise of the number of publications happened after these new efforts. In IEDM (International Electron Devices Meeting), a world reference in the subject, many contributions have been received in the last few years. A huge number of research centres and company Labs are currently working on the subject. This is the reason why we present this doctoral thesis proposal. If the non-volatile memories of the future are made with RRAMs, the current electronic technology landscape would change dramatically: new electronic applications would appear and even new computer architectures that could use the advantages of having large amounts of non-volatile memory, including to the extreme of replacing volatile memories in their usual functions. This technology is simple, it consists of structures of two terminals of nanometric size that offers very low currents of programming and erase, high speed, high durability (endurance) and viability for the integration in CMOS technologies and the manufacture of structures stacked in 3D [Lanza2019, Munjal2019, Gupta2019, Carboni2019, Xie2014, Waser2007, Waser2012, Zahurak2014]. A RRAM memory is usually manufactured with a MIM (Metal-Insulator-Metal) structure although they have also been manufactured with MIS (Metal-Insulator-Semiconductor) structures. In RRAM structures, an insulating material is usually placed between the two electrodes; In general, this material is an oxide that the electrical conduction properties can be changed as a result of the transport of ions in its core. RS phenomena have been observed in many different materials [Lanza2019, Munjal2019, Gupta2019, Carboni2019, Waser2012]: 1.- Transition metal oxides (transition metal oxides, TMOs), for example: TiO2, Cr2O3, FeOx and NiO. 2.- TMO of the perovskite family that have paraelectric, ferroelectric, multiferroelectric and magnetic functionality, for example: (Ba, Sr) TiO3, Pb (ZrxTi1-x) O3, BiFeO3 and PrxCa1-xMnO3. 3.- High bandwidth prohibited materials: Al2O3, HfO2 and Gd2O3. 4.- Graphene oxides. The good results obtained at the device level have also recently been verified at the circuit level, where an integrated RRAM memory circuit of 16 GBs has been manufactured successfully by the company Sony [Zahurak2014] or a 32Gbits memory using a 24nm CMOS process, based in a MeOx RRAM device reported at [Liu2013] [Liu2014]. This fact makes it clear that the possibilities of these devices and the corresponding circuits are very promising. The RRAMs memories belong to a larger group of electronic devices: memristors [Chua1971, Chua2011, Kozma2012]. The functioning and existence of these devices were predicted at the end of the 1960s. They have great potential for applications ranging from non-volatile memories to the manufacture of neuromorphic circuits (circuits that analogically reproduce biological systems, particularly neuronal circuits). There are currently many technologies that serve to manufacture memristors; among others, RRAMs manufacturing technology, although the other types of emerging NVM discussed above such as MRAMs, PCMs and STT-RAMs are also memristors [Kozma2012]. In this doctoral thesis we have focused on the modeling of memristors implemented with different technologies. The models are used both for analog and digital applications. This doctoral thesis includes eight publications in scientific journals indexed in the Journal Citation Report of Science Citation Index, five Proceedings published in IEEE Xplore digital library and twelve contributions to International Conferences. The outline is the following: Chapter 1 show a review of the state of the art in the simulation context about the memristor. First, introduce the memristor element in the general non-linear circuit modeling, next the resistive switching devices is described in terms of different technologies used. The different levels of simulation of RRAM devices is discussed and the compact model is described and justified. The last section of this chapter, show the actual context application of memristor and RRAM devices. Chapter 2 introduced the main model used for compact modeling of Conductive Bridge RRAM (IM2NP-CBM and IM2NP-CBF) and present a new compact model (UGR-VCM). This model used a truncated-cone CF geometry and a temperature description with two temperatures (top and bottom), verified with a Ti/ZrO2/Pt RRAM device made of Lab of Nanofabrication and Novel Device Integration, Institute of Microelectronics, Chinese Academy of Sciences. For tested the potential applications as memory, a simple 1T1R architecture is used for simulation purposes. This chapter include the contribution Gonzalez-Cordero et al. [González-Cordero2016a], “A new compact model for bipolar RRAMs based on truncated cone conductive filaments, a Verilog-A approach,” Semiconductor Science and Technology, vol. 31, no. 11, pp. 1–13, 2016. DOI: 10.1088/0268-1242/31/11/115013. Chapter 3 deal about the Valence Change Memories. A review of more important models of this kind of memories was shown: the unidimensional compact model for VCM bipolar RRAM (SU-VCM) and the bidimensional compact model for VCM bipolar RRAM (PU-VCM). In this context, a new model for bipolar resistive RRAMs UGR-VCM is presented, based on redox and diffusion processes to describe in detail the physics behind the filamentary resistive switching (RS) mechanisms under study. Includes truncated-cone shaped filaments which are known to be close to the real conductive filament geometry and a detailed thermal approach. The new model is tested with different technologies and the variability of cycle to cycle is included in the model. This chapter include the followings contributions: ▪ González-Cordero et al. [González-Cordero2017a], “In-depth study of the physics behind resistive switching in TiN/Ti/HfO2/W structures”, Journal of Vacuum Science and Technology B. 35, 01A110 (2017). DOI: 10.1116/1.4973372. ▪ González-Cordero et al. [González-Cordero2017d], “A Physically Based Model to describe Resistive Switching in different RRAM technologies”, in 11th edition of the Spanish Conference on Electron Devices (CDE), 2017 in Barcelona, Spain. DOI: 10.1109/CDE.2017.7905223 ▪ González-Cordero et al. [González-Cordero2017b], “A physically based model for resistive memories including a detailed temperature and variability description”, Microelectronic Engineering, Volume 178, 25 June 2017, Pages 26-29. DOI: 10.1016/j.mee.2017.04.019 Chapter 4 focuses on devices with unipolar switched resistance, this chapter present previous models (IM2NP-U and QPC) and two new QPC models: UGR-QPC1 and UGR-QPC2 with different thermal description approximations (thermal resistance variable and thermal capacity variable respectively). A new technique of extraction of characteristics of the QPC model based on second derivative of current is presented and introduced. This chapter include the followings contributions: ▪ Roldán et al. [Roldán2018] “Multivariate analysis and extraction of parameters in resistive RAMs using the Quantum Point Contact model” Journal of Applied Physics, 2018, 123, 014501. DOI: 10.1063/1.5006995. ▪ González-Cordero et al. [González-Cordero2016e], “A Physically Based Model to describe Resistive Switching in different RRAM technologies”, in 11th edition of the Spanish Conference on Electron Devices (CDE), 2017 in Barcelona, Spain. DOI: 10.1109/CDE.2017.7905223. ▪ Jiménez-Molinos et al. [Jiménez-Molinos2017], “SPICE modelling of thermal reset transitions for circuit simulation”, in 11th edition of the Spanish Conference on Electron Devices (CDE), 2017 in Barcelona, Spain. DOI: 10.1109/CDE.2017.7905227. Chapter 5 study the Random Telegraph Noise in RRAM devices. Review the graphical methods of representation and proposes two new methods: LWTLP and dLWTLP that presents a high computational efficiency in comparation with the previous ones. The methods are used to represent long time sequences of RTN, and finally an application of LWTLP technique is presented, with Neural Network Based Analysis of RTN with LWTLPfor classified RTN traces with help us Set Organization Memory is presented. This chapter include the followings contributions: ▪ González-Cordero et al. [González-Cordero2019a], “New method to analyze random telegraph signals in resistive random access memories” Journal of Vacuum Science and Technology B. 37, 012203 (2019). DOI: 10.1116/1.50593840. ▪ González-Cordero et al. [González-Cordero2019c], “A new technique to analyze RTN signals in resistive memories” Microelectronic Engineering, Volume 215, 15 July 2019, 110994 DOI: 10.1016/j.mee.2019.110994 ▪ Gonzalez-Cordero et al. [González-Cordero2019d], “Neural network based analysis of Random Telegraph Noise in Resistive Random Access Memories,” Semiconductor Science and Technology. DOI: 10.1088/1361-6641/ab6103 Chapter 6 describe simulations of resistive switching memristor with different models implemented in this thesis in different circuits, based on analog and digital applications. For example, 1T1R and 3x3 matrix memory in digital applications and controlling the conductance of a device that can be used as electronic synapses in an analog application. This chapter include the followings contributions: ▪ González-Cordero et al. [González-Cordero2016f], “Simulation of RRAM memory circuits, a Verilog-A compact modeling approach,” Proceedings of IEEE of the Design of Circuits and Integrated Systems Conference (DCIS), 2016 in Granada, Spain. DOI: 10.1109/DCIS.2016.7845386 ▪ González-Cordero et al. [González-Cordero2017c], “SPICE simulation of RRAM circuits. A compact modeling perspective”, in 11th edition of the Spanish Conference on Electron Devices (CDE), 2017 in Barcelona, Spain. DOI: 10.1109/CDE.2017.7905250 ▪ González-Cordero et al. [González-Cordero2019b], “A physical model to describe electronic synapses based on resistive switching devices” Solid State Electronics, Volume 157, July 2019, Pages 25-33. DOI: 10.1016/j.sse.2019.04.001 Chapter 7 show the main conclusions of this thesis. Appendix A describe the fabrication process and measurement set-ups for the different experimental devices used in this thesis. Appendix B and C introduced additional development used to modeling CB-RAM and VCM models respectively. And finally, Appendix D present different thermal descriptions approaches reported in the literature and present some new approaches used in this thesis.7 References [Carboni2019] Carboni, R., & Ielmini, D. (2019). Stochastic Memory Devices for Security and Computing. Advanced Electronic Materials, 5(9), 1900198. DOI: 10.1002/aelm.201900198 [Chua1971] L. Chua, “Memristor-The missing circuit element”, IEEE Transactions on Circuit Theory, vol. 18, nº 5, pp. 507-519, Sep 1971. DOI: 10.1109/TCT.1971.1083337 [Chua2011] L. Chua, “Resistance switching memories are memristors”, Appl. Phys. A, vol. 102, nº 4, pp. 765-783, jan 2011. DOI: 10.1007/s00339-011-6264-9 [González-Cordero2016a] G. González-Cordero, J. B. Roldan, F. Jimenez-Molinos, J. Suñé, S. Long and M. Liu, “A new compact model for bipolar RRAMs based on truncated cone conductive filaments, a Verilog-A approach,” Semicond. Sci. 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